We have currently 4 Digital Design Engineers in our Digital Design
team.
Years of Digital Design experience: 5, 5,
7 and 9 years.
RTL languages:
VHDL, Verilog and SystemVerilog.
Two
Engineers have experience in Chisel and SpinalHDL too.
All
our Engineers are also skilled in SVN, Git, Jira and
scripting languages like Python or TCL.
Communication systems (buses, communication protocols)
CPU architecture
and microarchitecture (RISC-V)
Security (cryptography,
authentication, security protocols)
Real-time embedded systems
(automotive, avionics, space)
Low-power design (energy harvester
control units)
Operating system kernel (task scheduling, memory
management units)
and many more!
We have currently
4 Verification Engineers in our Verification team.
Years of Verification experience: 2, 4,
5 and 11 years.
Verification languages: VHDL,
Verilog, SystemVerilog and
SystemC.
All four Engineers have also experience with
OVM, UVM, HW
testing and object-oriented programming.
The most preffered simulator is ModelSim or
QuestaSim but other simulators can be used as well.
All our
Engineers are also skilled in SVN, Git,
Jira and scripting languages like Python or TCL.
Communication systems (buses, communication protocols)
CPU architecture and microarchitecture (RISC-V)
Security (cryptography, authentication, security protocols)
Real-time embedded systems (automotive, avionics, space)
Low-power design (energy harvester control units)
Operating system kernel (task scheduling, memory management
units)
and many more!
The RTL part of ASIC (i.e. frontend) is handled by our Digital Design team.
The
physical design part of ASIC (i.e. backend) is handled by our Physical
Design team, which consists of 1 Physical Design Engineer at the
moment.
Years of Physical Design experience: 8
years.
In case of mixed-signal chip design, we have
a team of 4 Analog Design Engineers.
Years of Analog Design
experience: 3, 3, 6 and 11
years.
All our Engineers are also skilled in SVN, Git,
Jira and scripting languages like Python or TCL.
Physical Design tools: Cadence (Genus, Innovus, Tempus, Conformal,
etc.)
ASIC technologies used so far, for both digital and mixed-signal design:
TSMC (28 nm, 90 nm,
110 nm and 130 nm)
Low-power
design, including usage of subtreshold power supply and bulk-driven
CMOS circuits.
Automatic layout for digital design and manual
layout for digital or mixed-signal design.
The RTL part of FPGA
(i.e. frontend) is handled by our Digital Design team.
The implementation part of FPGA (i.e. backend) is handled by our
FPGA team, which consists of 2 FPGA Engineers at the moment.
Years of FPGA experience: 3 and 4 years.
All
our Engineers are also skilled in SVN, Git, Jira and
scripting languages like Python or TCL.
We have experience with
Xilinx and Intel (formerly Altera)
FPGA, including SoC versions that also contain hard-core CPUs on
chip.
IP cores integration, static timing analysis
(STA), pin mapping, clock management, JTAG
debugging and HW testing are included too.
We have currently
2 Embedded Software Engineers in our Embedded Software team.
Years of Embedded Software experience: 3 and 22
years.
Programming languages: C, C++ and assembly
language.
All our Engineers are also skilled in
SVN, Git, Jira and scripting
languages like Python or TCL.
Programming for RISC CPUs (ARM, RISC-V) or CISC CPUs
(x86).
Available also for CPUs in FPGA or SoC devices.
Programs
can run on Linux, real-time operating systems or
bare-metal.